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Espressif Systems /ESP32-P4 /AXI_DMA /IN_CONF0_CH1

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Interpret as IN_CONF0_CH1

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (IN_RST_CH)IN_RST_CH 0 (IN_LOOP_TEST_CH)IN_LOOP_TEST_CH 0 (MEM_TRANS_EN_CH)MEM_TRANS_EN_CH 0 (IN_ETM_EN_CH)IN_ETM_EN_CH 0IN_BURST_SIZE_SEL_CH 0 (IN_CMD_DISABLE_CH)IN_CMD_DISABLE_CH 0 (IN_ECC_AEC_EN_CH)IN_ECC_AEC_EN_CH 0 (INDSCR_BURST_EN_CH)INDSCR_BURST_EN_CH

Description

Configure 0 register of Rx channel 0

Fields

IN_RST_CH

This bit is used to reset AXI_DMA channel 0 Rx FSM and Rx FIFO pointer.
IN_LOOP_TEST_CH

reserved
MEM_TRANS_EN_CH

Set this bit 1 to enable automatic transmitting data from memory to memory via AXI_DMA.
IN_ETM_EN_CH

Set this bit to 1 to enable etm control mode, dma Rx channel 0 is triggered by etm task.
IN_BURST_SIZE_SEL_CH

3’b000-3’b100:burst length 8byte~128byte
IN_CMD_DISABLE_CH

1:mean disable cmd of this ch0
IN_ECC_AEC_EN_CH

1: mean access ecc or aes domain,0: mean not
INDSCR_BURST_EN_CH

Set this bit to 1 to enable INCR burst transfer for Rx channel 0 reading link descriptor when accessing internal SRAM.

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data